The present invention relates generally to a semiconductor device and method for its manufacture, and more specifically to a semiconductor device including an insulated gate field effect transistor (IGFET) having a particular gate electrode insulation structure and a method of its manufacture.
In order to reduce manufacturing costs and provide more components on a semiconductor device, semiconductor devices are being made with finer structures. Such components include insulated gate field effect transistors (IGFETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs). Semiconductor devices such as memory devices and logic devices are now being made in which minimum line widths are about 0.15 xcexcm.
As IGFETs become finer, the film thickness of the gate insulating film becomes finer. In such cases, the gate insulating film can be a silicon oxide film having a thickness of about several nanometers. In a conventional IGFET, such as a MOSFET structure, once the gate insulating film is made thinner, a steep band bending may occur on the surface of a drain region that is overlapped by and separated from the gate electrode by the gate insulating film. Although in this case, while the gate electrode may be biased so that the MOSFET is in the non-conduction state, a leakage current may be increased due to inter-band tunneling of electrons between a valence band and a conduction band. The tunneling occurring due to the above-mentioned band bending has been reported in xe2x80x9cInternational Electron Device Meeting (IEDM), 1987, pp. 718-721.xe2x80x9d
The above-mentioned tunneling phenomenon will now be described with reference to FIGS. 1A and 1B.
Referring now to FIG. 1A, a cross sectional view of a portion of a conventional N-channel MOSFET is set forth.
As illustrated in FIG. 1A, a silicon substrate having a P-type conductivity is connected to a ground potential. The potential Vg of a gate electrode is also connected to the ground potential. The gate electrode is separated from the substrate by a gate insulating film. A drain region having a n+ type conductivity is formed on the substrate surface. An electric potential Vd is applied to the drain region. Once the electric potential Vd is applied to the drain region, a depletion region (indicated by the dashed line) is formed at the p-n junction formed at the interface of the drain region and substrate. Holes and electrons may be produced in the depletion region. The electric field causes the positive holes to flow into the substrate and the negative electrons to flow into the drain region. In this way, a leakage current is caused by inter-band tunneling as mentioned above.
Referring now to FIG. 1B, a band diagram of an N-channel MOSFET and a P-channel MOSFET is set forth. The band diagram on the left illustrates a band diagram of an N-channel MOSFET as shown in FIG. 1A along the line X-Y. The band diagram on the right illustrates a band diagram along a similar line for a P-channel MOSFET.
In the case of the N-channel MOSFET, the band has a higher energy at the gate (G) and the energy is lowered across the gate insulating film (Ox) to the drain (D). As the gate insulating film (Ox) becomes thinner, a steep band bending occurs in the drain (D). Thus, electrons in the valence band may tunnel to the conduction band thereby forming holes in the valance band. This activity of the electrons flowing from the substrate to the drain and creating holes flowing to the substrate create a leakage current in the substrate.
In the case of the P-channel MOSFET, the band energy levels are reversed. Thus, the band has a lower energy at the gate (G) and the energy is increased across the gate insulating film (Ox) to the drain (D). As the gate insulating film (Ox) becomes thinner, a steep band bending occurs in the drain (D). Thus, electrons in the valence band may tunnel to the conduction band thereby forming holes in the valance band. This activity of the electrons flowing from the drain to the substrate and creating holes flowing to the drain create a leakage current in the substrate.
Japanese Laid-Open Patent Publication No. Hei 1-264264 (JP 1-264264) discloses a method for preventing such a leakage current due to inter-band tunneling. In JP 1-264264, inter-band tunneling is prevented by moderating the bending by altering a material to change the work function of the gate electrode in a region which overlaps the drain region. In this method, the gate electrode is constructed with conductor materials of different conductivity types in which the first conductivity type is used for the gate electrode over the channel area of the transistor and the second conductivity type is used for the gate electrode over the source-drain regions of the transistor. The conductor materials of different types are chosen such that their work functions are different from each other.
The present inventor has investigated, in detail, the leakage current caused by the above-mentioned inter-band tunneling in a semiconductor device using 256 Megabit and a 1 Gigabit Dynamic Random Access Memory technology.
The investigations have indicated that there appears to be a large influence in the leakage current caused by the above-mentioned inter-band tunneling. The influence of the leakage current is likely to appear when the drain voltage becomes relatively high, as in a voltage boosting circuit. In such a boosting circuit the inter-band tunneling phenomenon is typically found in P-channel MOSFETs instead of N-channel MOSFETs. Thus, in semiconductor devices there are transistors where inter-band tunneling may be problematic, but other transistors where inter-band tunneling may not occur. The present inventor has found that state of the art semiconductor devices may require a technique to optionally suppress inter-band tunneling depending upon the circuits in the semiconductor device in which the transistors are placed.
In the technique illustrated in JP 1-264264, use is made of different conductor materials for the gate electrode to suppress inter-band tunneling of a selected transistor. Such a technique may complicate the manufacturing process of the semiconductor device by increasing the number of processes to be performed during manufacturing. This may lower yield and may increase manufacturing costs.
In light of the above discussion, it would be desirable to provide a semiconductor device in which inter-band tunneling may be suppressed in selected transistors.
A semiconductor device according to the present embodiments may include an insulated gate filed effect transistor (IGFET) having a gate insulating layer, a gate electrode, and a source-drain layer. The IGFET may include a bird""s beak insulating film in a region in which the gate insulating layer overlaps the source-drain layer. The bird""s beak insulating film may have a thickness that is greater than the gate insulating film. In this way, inter-band tunneling may be reduced. A plurality of IGFETs may include bird""s beak insulating films having different configurations in accordance with operating conditions of the circuit in which the particular IGFET is included.
According to one aspect of the embodiments, a semiconductor device may include a first IGFET. The first IGFET may include a gate insulating film having a film thickness greater in a first region where a gate electrode overlaps a first source-drain diffusion layer than in a channel region.
According to another aspect of the embodiments, the gate insulating film may have a film thickness greater in a second region where the gate electrode overlaps a second source-drain diffusion layer than in the channel region.
According to another aspect of the embodiments, the gate insulating film may form a bird""s beak configuration where the gate insulating film may be thicker at the edge of the gate electrode.
According to another aspect of the embodiments, a second IGFET may have a second gate insulating film that does not have the bird""s beak configuration.
According to another aspect of the embodiments, the source-drain diffusion layer may have a lightly doped drain (LDD) structure.
According to another aspect of the embodiments, the bird""s beak configuration may be formed on the gate insulating film with a heat treatment in an oxidation atmosphere after the gate electrode is formed.
According to another aspect of the embodiments, a semiconductor device may include a first IGFET including a first IGFET gate insulating film, a first IGFET gate electrode, a first IGFET source-drain diffusion layer, and a first IGFET channel region. A first bird""s beak insulating film may be formed in a first region where the first IGFET gate electrode overlaps the first IGFET source-drain region. The first bird""s beak insulating film may have a thickness greater than the first IGFET gate insulating film. A second IGFET may include a second IGFET gate insulating film, a second IGFET gate electrode, a second IGFET source-drain diffusion layer, and a second IGFET channel region. A second bird""s beak insulating film may be formed in a second region where the second IGFET gate electrode overlaps the second IGFET source-drain region. The second bird""s beak insulating film may have a thickness greater than the second IGFET gate insulating film. The first bird""s beak insulating film may have a different configuration than the second bird""s beak insulating film.
According to another aspect of the embodiments, first bird""s beak insulating film may be formed on the gate insulating film with a heat treatment in an oxidation atmosphere after the first IGFET gate electrode is formed.
According to another aspect of the embodiments, the first IGFET source-drain diffusion layer may be an LDD structure.
According to another aspect of the embodiments, the first IGFET may be a N-type IGFET and the second IGFET may be a P-type IGFET.
According to another aspect of the embodiments, the first bird""s beak insulating film may have a first film thickness. The second bird""s beak insulating film may have a second film thickness. The second film thickness may be greater than the first film thickness.
According to another aspect of the embodiments, the first bird""s beak insulating film may have a first penetration depth under the first gate electrode. The second bird""s beak insulating film may have a second penetration depth under the second gate electrode. The second penetration depth may be greater than the first penetration depth.
According to another aspect of the embodiments, a method of manufacturing a semiconductor device may include the steps of forming a first gate insulating film on the surface of a semiconductor substrate, forming a first gate electrode on the first gate insulating film, and introducing an impurity in a region around the first gate electrode for enhancing the speed of thermal oxidation. The first gate electrode may have a first gate width defined by a first first gate edge and a second first gate edge. The method may include the step of forming a first bird""s beak insulating film under the first gate electrode at the first first gate edge and a second first gate edge.
According to another aspect of the embodiments, forming the first bird""s beak insulating film may include heat treating the semiconductor substrate in an oxidation atmosphere.
According to another aspect of the embodiments, forming the first gate electrode may include forming a conductor film for covering the gate insulating film by depositing a first conductivity type polycrystalline silicon film.
According to another aspect of the embodiments, introducing the impurity may include introducing atoms of at least one of the group consisting of phosphorus, arsenic, halogen, or inert gas.
According to another aspect of the embodiments, introducing the impurity may include a tilt ion implantation.
According to another aspect of the embodiments, the method of manufacturing the semiconductor device may include the step of forming a second gate electrode. The second gate electrode may have a second gate width defined by a first second gate edge and a second second gate edge. The method of manufacturing the semiconductor device may include the step of forming a second bird""s beak insulating film under the second gate electrode at the first second gate edge and the second second gate edge. The first bird""s beak insulating film may have a different configuration than the second bird""s beak insulating film.
According to another aspect of the embodiments, the first gate electrode may be a first IGFET gate electrode. The second gate electrode may be a second IGFET gate electrode. Introducing an impurity in the region around the first electrode includes introducing the impurity having a different dosage in a second region around the second gate electrode than in the region around the first gate electrode.
According to another aspect of the embodiments, the first IGFET may be a N-type MOSFET and the second IGFET may be a P-type MOSFET.